Institute of Electrical & Electronic Engineers
With recent developments in transmission technologies, more demanding performance characteristics are being sought when designing routers. The previously centralized router devices with a single general-purpose processor cannot cope with the ever-increasing workloads and are being replaced by routers with more effective architectures, i.e. distributed or parallel. A novel scheme for processing packets in a router is presented that provides load sharing among multiple network processors distributed within the router. It is complemented by a feedback control mechanism designed to prevent processor overload. Incoming traffic is scheduled to multiple processors based on a deterministic mapping.