Adaptive Router Design for Networks-on-Chip on FPGA Using Buffer Resize Technique

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Provided by: International Journal of Engineering Trends and Technology
Topic: Hardware
Format: PDF
Compared to buses, Network-on-Chip (NoC) have a relative area and delay overhead. These can be reduced in application specific systems where heterogeneous communication infrastructure provide high bandwidth in a localized fashion and reduce under-utilized resources. For general purpose systems, design time techniques are not efficient. One important technique for improving area and/or performance of NoCs for general purpose systems is to consider dynamic adaptation of the resources at runtime. This paper proposes the adaptive buffer resize technique for NoCs.
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