International Journal of Engineering Trends and Technology
The fast spread of wireless data communication systems and the ever increasing demand for faster data rates requires fast design, implementation and test of new wireless algorithms and architectures for data communications. The most popular communication decoder, the Turbo decoder, requires an exponential increase in hardware complexity to achieve greater decoding accuracy. Interleaver is a critical component of a turbo decoder. In this paper, first utilize the balanced scheduling scheme to avoid memory reading conflicts. Then, based on the statistical property of memory conflicts, the other critical parameters access timing, power and area are reduced when using another alternative for the IAG which is FSM based IAG (Interleaver Address Generator).