Address Generation Circuitry of WiMAX Deinterleaver Using Xilinx FPGA
In this paper, the authors report the implementation of address generator of the 2-D deinterleaver used in WiMAX transreceiver system using FPGA. The bit streams in channel inter-leaver and deinterleaver for IEEE 802.16e standard associated with floor function is very difficult to implement on the FPGA kit. But by using this proposed algorithm eliminates the requirement of floor function and it also reduces the complexity in the FPGA implementation. In this paper, they presents a novel and highly efficient Quadrature Phase Shift Keying (QPSK), 16-QAM, 64-QAM sharing resources and these are novel and highly efficient compared with conventional Look-Up-Table (LUT) based approach.