There are so many strategies implemented to reduce the power consumption in CMOS digital design. Many of them are based on complement form and clock signals. In CMOS digital design power consumption can be reduced by reducing the supply voltage, decreasing capacitance and reducing the switching activities. These techniques are not suitable in today's CMOS design scenario. So many researchers are working on new design techniques which will help in reducing the dynamic power consumption. Most of the research is focused on adiabatic logic which is proved to be the excellent technique to design the low power digital circuits.