Algorithm Parallelism Estimation for Constraining Instruction-Set Synthesis for VLIW Processors

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Provided by: Eindhoven University of Technology
Topic: Hardware
Format: PDF
Customization of a (generic) processor to a particular application makes it possible to achieve high performance within a tight energy budget. Most of the published research works on processor customization extend a simple base processor with custom instructions. Only few works have considered a full instruction-set customization for complex highly parallel Very Long Instruction Word (VLIW) architectures. This paper discusses the parallelism estimation for a full instruction-set synthesis for VLIW processors and evaluates four methods to compute the maximum parallelism of a given application.
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