An 8 Bit 4 GS/s 120 mWCMOS ADC

For a given resolution, the power consumption of Analog-to-Digital Converters (ADCs) rises linearly with the speed up to some point and then begins to ascend at an increasingly higher rate. A time-interleaved ADC employs four pipelined time-interleaved channels along with a new timing mismatch detection algorithm and a high-resolution variable delay line. The digital background calibration technique suppresses the inter-channel timing mismatches, achieving an SNDR of 44.4dB and a figure of merit of 219fJ/conversion-step in 65nm CMOS technology.

Provided by: Institute of Electrical and Electronics Engineers Topic: Hardware Date Added: Aug 2014 Format: PDF

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