Institute of Electrical & Electronic Engineers
In this paper, the authors present the hardware architecture of DynaCORE, a dynamically reconfigurable system-on-chip for network applications. DynaCORE is an application specific coprocessor for offloading computationally intensive tasks from a network processor. The System-on-Chip (SoC) architecture is based on an adaptable Network-on-Chip (NoC) which allows the dynamic replacement of hardware modules as well as the adaptation of the on-chip communication structure. The co-processor leverages the active partial reconfiguration feature of modern FPGAs in order to adapt to shifting demand patterns.