An Advanced and More Efficient Built-In Self-Repair Strategy for Embedded Sram with Selectable Redundancy

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Provided by: IJCTT-International Journal of Computer Trends and Technology
Topic: Storage
Format: PDF
Built-In Self-Test (BIST) refers to those testing techniques where additional hardware is added to a design so that testing is accomplished without the aid of external hardware. Usually, a pseudo-random generator is used to apply test vectors to the circuit under test and a data compactor is used to produce a signature. To increase the reliability and yield of embedded memories, many redundancy mechanisms have been proposed. All the redundancy mechanisms bring penalty of area and complexity to embedded memories design. To solve the problem, a new redundancy scheme is proposed in this paper.
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