An Algorithm for Leakage Power Reduction Through IVC in CMOS VLSI Digital Circuits

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Provided by: International Journal of Computer Applications
Topic: Hardware
Format: PDF
Leakage current in CMOS circuits can be controlled at the circuit level and at the device level as well. One of the circuit level control techniques is the Input Vector Control (IVC). By using IVC, leakage power consumption of a circuit can be reduced in the sleep state. In this paper, an algorithm has been given to determine the optimum input vector that can be applied to the circuit in the sleep state for getting low leakage power. This algorithm uses the concept of controllability of the nodes in the circuit and the dependency of a gate on the remaining gates in the circuit to determine the optimum input vector.
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