An Alternative Logic Approach to Implement Energy Efficient 90-Nm CMOS Full Adders

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Provided by: Creative Commons
Topic: Hardware
Format: PDF
In this paper, the authors present power analysis of the seven full adder cells reported as having a low PDP (Power Delay Product), by means of speed, power consumption and area. In this paper, they present two proposed high-speed and low-power full-adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced Power Delay Product (PDP). The existed standard full adders and the proposed full adders are designed and showed the better result comparison.
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