The MOS Current Mode Logic (MCML) is becoming further accepted due to it dissipates less power than conventional CMOS circuits at high frequency. MCML is also analyzed for submission to low power as well as mixed signal atmosphere. The architecture of 8-bit by8-bit MCML multiplier is projected and the operation is explained for high speed applications supported by its simulation result. All simulations are performed on 0.6 standard CMOS double metal double poly process, using CADENCE design tool (Virtuoso). Here in this paper, a MCML 8-bit by 8-bit multiplier cell library is developed and optimized for numerous different performance desires.