University of Florence
Semiconductor transient faults have become an increasingly important threat to microprocessor reliability. Simultaneous Multi-Threaded (SMT) architectures exploit thread-level parallelism to improve overall processor throughput. A great amount of research has been conducted in the past to investigate performance and power issues of SMT architectures. Nevertheless, the effect of multithreaded execution on a microarchitectures vulnerability to soft error remains largely unexplored. In this paper, the authors have developed a microarchitecture level soft error vulnerability analysis framework for SMT architectures.