University of Vigo
Process variations are one of the biggest obstacles to overcome for high performance SRAM designs. One of the places worst affected is the timing of the \"Strobe,\" referring to the Sense Amp (SA) enable, a signal whose transition indicates that a sufficient voltage differential has developed on the Bit-Lines (BLs) to allow the read operation to complete correctly. This BL development dominates the delay of an SRAM's read operation, which is usually slower than write. Setting the timing of the strobe represents a difficult tradeoff, since the designer must ensure that the effects of process variation in either the bitcell's read current (IREAD) and/or the SA's intrinsic input referred Voltage OffSet (VOS) do not cause false values to be read from the bitcell.