A multiplier is widely used in digital signal processing such as in filters and in computer hardware design. It is generally needed in carrying out complex computations and as such affects the devices' performance in terms of speed, cost, flexibility, on-chip area, etc. Thus, to design a multiplier with best possible efficiency in terms of speed, cost, on-chip area, etc. is the need of the day. In this paper an attempt has been made to design a multiplier based on ancient Indian mathematics (Vedic mathematics). It has been designed using Xilinx ISE 8.2i.