Institute of Electrical & Electronic Engineers
In Chip Multi-Processor (CMP) systems with multi-application workloads, communication and memory access both play an important role in influencing system performance. Intelligently prioritizing network packets and memory requests can notably improve system throughput. But with increasing workload diversity in CMPs, applying the same request prioritization rules across the chip can lead to sub-optimal results. In this paper, the authors propose a novel heterogeneous prioritization framework for CMPs in which two different packet prioritization approaches are proposed and applied to Network-on-Chip (NoC) routers.