Provided by: Georgia Institute of Technology
Date Added: May 2011
Given a 16-bit or 32-bit overclocked ripple-carry adder, the authors minimize error by allocating multiple supply voltages to the gates. They solve the error minimization problem for a fixed energy budget using a Binned Geometric Program Solution (BGPS). A solution found via BGPS outperforms the two best prior approaches, uniform voltage scaling and biased voltage scaling, reducing error by as much as a factor of 2.58x and by a median of 1.58x in 90nm transistor technology.