Institute of Electrical & Electronic Engineers
The authors propose the use of a novel architecture, called the Multi-Level Computing Architecture (MLCA) to efficiently exploit coarse-grain parallelism on FPGAs. The central component of the MLCA is its Control Processor (CP), which is analogous to an out-of-order scheduling unit of a superscalar processor. The CP schedules coarse-grain units of computation, or tasks, onto Processing Units (PUs). In this paper, they explore the FPGA implementation of the CP and demonstrate the scalability of the MLCA for multimedia applications. They design, test and evaluate an 8-PU MLCA system.