An Architecture for Low-Power High-Performance Embedded Computing

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Provided by: University of Miami School of Business Administration
Topic: Hardware
Format: PDF
There are a growing number of systems that require high-performance low-power embedded solutions. Recently the DARPA PERFECT program set forth an efficiency goal of 75 GFLOPS/W to enable embedded computing in Unmanned Aerial Vehicles (UAVs). As a result of analyzing a typical UAV workload, Wide-Angle Motion Imaging (WAMI), the authors are able to specify a new architecture to enable as much computing on board the UAV as possible. This paper presents the proposed heterogeneous architecture, which includes: accelerators to enable extreme energy-efficiency for key kernels; throughput accelerators, such as GPGPUS or SIMD engines, for highly parallel work; near-threshold parallel general purpose processors to facilitate path-divergent parallel code; and voltage boosting techniques to improve the speed of the general purpose processors to enable single-thread computation.
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