An Architecture-Level Approach for Mitigating the Impact of Process Variations on Extensible Processors

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Provided by: edaa
Topic: Hardware
Format: PDF
In this paper, the authors present an architecture-level approach to mitigate the impact of process variations on extended Instruction Set Architectures (ISAs). The proposed architecture adds one extra cycle to execute Custom Instructions (CIs) that violate the maximum allowed propagation delay due to the process variations. Using this method, the parametric yield of manufactured chips will greatly improve. The cost is an increase in the cycle latency of some of the CIs, and hence, a slight performance degradation for the extensible processor architectures.
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