International Journal of Soft Computing and Engineering (IJSCE)
The performance of flip-flop is an important element to determine the efficiency of the whole synchronous circuit. This paper presents an efficient explicit pulsed static single edge triggered flip flop with an improved performance and overcomes the drawbacks of the implicit type pulsed flip flops. The proposed flip flop is having a structure of explicit pulse-triggered with a modified true single phase clock latch based on signal feed through scheme. The proposed flip-flop is compared with existing explicit pulsed single edge triggered flip-flops in terms of power, speed and area.