An Area-Efficient Partially Reconfigurable Crossbar Switch with Low Reconfiguration Delay

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Provided by: National University of Singapore
Topic: Hardware
Format: PDF
With the increasing number of processors in Multi-Processor System-on-Chips (MPSoCs), Network-on-Chips (NoCs) are replacing conventional buses as the interprocessor communication architecture. Since different use cases might be running on MPSoCs, there is a need for dynamically reconfigurable NoC. However, most dynamically reconfigurable NoCs have a large area overhead due to the additional reconfiguration logic. While recently some dynamically reconfigurable NoCs have been proposed based on partial reconfiguration (PR), they have high reconfiguration delay and require off-line bit stream generation for all possible scenarios.
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