An Array Allocation Scheme for Energy Reduction in Partitioned Memory Architectures

In this paper the authors present a compiler technique that reduces the energy consumption of the memory sub-system, for an off-chip partitioned memory architecture having multiple memory banks and various low-power operating modes for each of these banks. More specifically, they propose an efficient array allocation scheme to reduce the number of simultaneously active memory banks, so that the other memory banks that are inactive can be put to low power modes to reduce the energy. They model this problem as a graph partitioning problem, and use well known heuristics to solve the same.

Provided by: Springer Healthcare Topic: Storage Date Added: Jan 2007 Format: PDF

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