An ASIC Implementation of the MP3 Decoder for a DAB and MP3 Combined Chip

In this paper, the authors propose an ASIC Implementation of the MP3 decoder for a MP3 and DAB combined chip in this paper. This MP3 decoder designed in pure hardware approach has the advantages high integration and low power consumption. Due to the system structure optimization and hardware sharing with the DAB audio decoders, the decoder only costs extra 30275 logic gates and 2976 ROM bytes, which occupies extra 0.37 mm2 silicon area for 1P4M 0.18 um CMOS technology.

Provided by: AICIT Topic: Hardware Date Added: Feb 2013 Format: PDF

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