An Efficient 32 -Bit Online Error Detection & Correction Scheme for Embedded Memory

Provided by: International Journal of Emerging Technology and Advanced Engineering (IJETAE)
Topic: Mobility
Format: PDF
As technology scales, VLSI performance has experienced an exponential growth. As feature sizes shrink, however, the authors will face new challenges such as soft errors (single-event upsets) to maintain the reliability of circuits. Recent studies have tried to address soft errors with error detection and correction techniques such as error correcting codes and redundant execution. However, these techniques come at a cost of additional storage or lower performance. Soft errors are a major reliability concern for today's nano-metre technologies. The errors in register files in Application Specific Integrated Circuits (ASIC) can quickly spread to various parts of the system and result in data corruption which may go unnoticed.

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