An Efficient Adiabatic 2:1 Multiplexer Design Approach for Low Power Applications
As in designing of conventional Complementary Metal-Oxide-Semiconductor (CMOS) logic, the power dissipation directly change with the variation in supply voltage. In this paper, authors have compared two adiabatic logic designs with conventional CMOS.A 2:1 multiplexer is implemented by these techniques and results are compared such as power dissipation, rise time and fall time. Transistor count and maximum frequency. The designing of schematic and simulation of these logics done on TANNER v7. From results it is found that power consumption of PFAL logic is less as compare to ECRL and CMOS.