Applications of Engineering Technology and Science (AETS)
In this paper, the authors represent a dual mode logic circuit for low power applications. Now-a-days, power consumption is the major role in chip design. If the area of the chip is reduced, the power consumption and the delays are increased due to some effects like, cross talk, process variation and channel effects of MOS devices. The CMOS logics are most used in logic design. But, it has some disadvantages related with power consumption. So, they can go to the dual mode logic. The proposed logic is operated between static mode and dynamic mode.