An Efficient Design of VLSI Architecture Based ML Decoder/Detector in Fault Detection

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Provided by: IJESIT
Topic: Security
Format: PDF
To prevent soft errors from causing data corruption, memories are typically protected with error correction codes. An advanced error correction codes are used when an additional protection is needed. The majority logic decoder/detector codes are used for memory application because of correcting large number of soft errors, less decoding time, area consumption. The differences set cyclic codes are suitable for error correction using majority logic decoder/detector. Because the difference set cyclic codes are small, powerful and easily implemented in terms of decoding latency and complexity and this design achieving very high data rate while minimizing complexity.
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