In recent years, memory cells have become more susceptible to soft errors. This must be protected with effective error correction codes. Majority logic decodable codes are suitable for memory applications because of their capability to correct large number of errors. Conversely, they increase the average latency of the decoding process because it depends upon the code size that impacts memory performance. Another method of decodable logic is majority logic decoder/detector which reduces the decoding time, memory access time and area utilization.