An Efficient FFT Processor Architecture with Optimised Area and Speed

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Provided by: International Journal of Modern Engineering and Research Technology (IJMERT)
Topic: Hardware
Format: PDF
It is required to design a very high-performance FFT processor to satisfy the desires of real time with low cost in many different systems. So paper presents a radix-2 FFT processor based implemented Field Programmable Gate Array (FPGA) which can work for Wireless Local Area Networks (WLANs) is proposed. Different than being stored in the conventional ROM, the twiddle factors in proposed FSM based FFT processor can be given directly. A unique and easy address mapping scheme proposed. The FFT processor has five different FSM stages. Finally, the pipelined 8-point proposed FFT processor can be completely implemented within only 637 slices only.
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