An Efficient High-Speed 9-Bit Parity Checker Using 4-2 Compressors

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Provided by: Creative Commons
Topic: Hardware
Format: PDF
In this paper, an efficient and simple implementation of 9-bit parity checker design using 4-2 compressors is presented; for generation of quick results of parity, especially for use in communications while transmission of binary message data from a transmitter side to a receiver side. Parity checkers are used for single bit error detection in the receiver end. The parity checkers detects both odd and even parity bits and is used as monitoring devices on high speed communication lines.
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