An Efficient Implementation of 4X4 Vedic Multiplier Using Power Gating Method

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Provided by: IRD India
Topic: Hardware
Format: PDF
In this paper, the authors propose a various multipliers implemented using CMOS logic style and their comparative analysis on the basis of power and PDP (Power Delay Product). A variety of multipliers have been reported in the literature but power dissipation and area used by these multiplier circuits are relatively large. This paper proposed a high performance and power efficient 8x8 multiplier design based on Vedic mathematics using CMOS logic style. In this paper, XNOR gates with MTCMOS and without MTCMOS technique are compared taking power consumption as parameter by varying voltage, frequency and temperature.
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