An Efficient Implementation of a High Performance Multiplier Using MT-CMOS Technique

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Provided by: IRD India
Topic: Hardware
Format: PDF
A variety of multipliers have been reported in the literature but power dissipation and area used by these multiplier circuits are relatively large. This paper proposed a high performance and power efficient 8x8 multiplier design based on Vedic mathematics using CMOS logic style. In this paper, XNOR gates with MTCMOS and without MTCMOS technique are compared taking power consumption as parameter by varying voltage, frequency and temperature. The designs are tested in 45nmtechnology. The XNOR gate design with MTCMOS technique gives least power consumption.
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