An Efficient Implementation of a Reversible Single Precision Floating Point Multiplier Using 4:3 Compressor

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Provided by: Reed Elsevier
Topic: Hardware
Format: PDF
In this paper, the authors propose an efficient design of a reversible single precision floating point multiplier based on compressor. The single precision floating point multiplier requires the design of an efficient 24x24 bit integer multiplier. In the proposed architecture, the 24x24 bit multiplication operation is fragmented to nine parallel reversible 8x8 bit multiplication modules. In this paper, a new reversible design of the 24x24 bit multiplier has been proposed which has been optimized in terms of critical path delay and garbage outputs.
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