An Efficient Implementation of High Performance Floating Point Adder / Subtractor

Floating Point (FP) arithmetic is widely used in large set of scientific and signal processing computation. adder/subtractor is one of the common arithmetic operations in these computations. This paper implements an efficient high performance floating-point adder/subtractor. The whole design was captured in Verilog Hardware Description Language (VHDL) and targeted on a Virtex-6 Xc6vlx75t-3ff484 Field Programmable Gate Array (FPGA), with optimal area and high performance. In addition, the proposed design is in compliant with IEEE-754 format and handles overflow, underflow and various exception conditions. This design operates at 331.939 MHz frequency.

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International Journal of Engineering, Science and Innovative Technology (IJESIT)