An Efficient Implementation of Multiplexer Based Flip-Flop in Subthreshold Region

Digital circuits operating in sub-threshold use a supply voltage that is less than the threshold voltages of the transistors. In this region of operation, they consume less energy for active operation and they dissipate less leakage power than higher voltage alternatives, but they operate more slowly. In this paper, two different flip-flop topologies in subthreshold region of operation are examined. Designs are simulated in 90 nm process with supply voltages ranging from 200 mV to 600 mV. Ultra-low power can be achieved in subthreshold region. Propagation delays and power dissipation are measured across all corners.

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