An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions

Provided by: Universidad Politecnica de Madrid
Topic: Hardware
Format: PDF
Current superscalar processors use a Re-Order Buffer (ROB) to support speculation, precise exceptions, and register reclamation. Instructions are retired from this structure in program order, which may lead to significant performance degradation if a long latency operation blocks the ROB head. In this paper, a checkpoint-free out-of-order commit architecture is proposed, which replaces the ROB with a small structure called Validation Buffer (VB) from which instructions are retired as soon as their speculative state is resolved.

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