An Efficient Low Power Test for NoC(Network-on-Chip)

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Provided by: AICIT
Topic: Hardware
Format: PDF
In this paper, the authors propose the low power test framework for Network-on-Chip (NoC), which is based on embedded processor and on-chip network. The possibility of using embedded processor and on-chip network is introduced and evaluated with benchmark system to test the other embedded cores. A new generation method of test pattern is presented to reduce the power consumption of on-chip network, which is called don't care mapping and variable flit size application. The experimental results show that the embedded processor can be executed like the automatic test equipments, and the test time is reduced and the power reduction rate is about 37%.
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