An Efficient Synchronization Technique for Multiprocessor Systems On-Chip
In this paper, the authors explore optimization techniques of the synchronization mechanisms for MPSoCs based on complex interconnect (Network-on-Chip (NoC)), targeted at future mobile systems. They suggest the architecture of the memory controller optimized to minimize synchronization overhead. The proposed solution is based on the idea of performing synchronization operations which require the continuous polling of a shared variable, thus featuring large contention (e.g. spin locks), locally in the memory. They introduce a HW module, which augments the memory controller, the Synchronization-operation Buffer (SB), which queues and manages the requests issued by the processors.