An Efficient VLSI Architecture and FPGA Implementation of High-Speed and Low Power 2-D DWT for (9, 7) Wavelet Filter
In this paper, the authors present an efficient VLSI (Very-Large-Scale Integration) architecture of a high speed, low power 2-D Discrete Wavelet Transform computing. The proposed architecture, based on new and fast lifting scheme approach for (9, 7) filter in DWT, reduces the hardware complexity and memory accesses. Moreover, it has the ability of performing progressive computations by minimizing the buffering between the decomposition levels. The system is fully compatible with JPEG2000 standard. Their designs were realized in VHDL (Verilog Hardware Description Language) language and optimized in terms of throughput and memory requirements.