An Energy-Efficient 3D CMP Design With Fine-Grained Voltage Scaling

Provided by: edaa
Topic: Hardware
Format: PDF
Most research on Chip Multi-Processor (CMP) focused on finding sophisticated methods and strategies to improve system performance. In this paper, the authors propose an energy-efficient 3D-stacked CMP design by both temporally and spatially fine-grained tuning of processor cores and caches. In particular, temporally fine-grained DVFS is employed by each core and L2 cache to reduce the dynamic energy consumption, while spatially fine-grained DVS is applied to the cache hierarchy for the leakage energy reduction. Their tuning technique is implemented by integrating an array of on-chip voltage regulators into the original processor.

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