An Energy-Efficient 64-Bit Prefix Adder Based on Semidynamic and Bypassing Structures
An energy-efficient 64-bit prefix adder is proposed for micro-server processors based on both semi-dynamic and bypassing structures. Prefix adders consist of three main stages i.e. Propagate-Generate (PG) stage, Carry Merge (CM) tree, and sum generators. In this architecture, the PG and CM stages consume most of the power because these are based on domino circuits. This paper proposes a semi-dynamic PG stage for its energy-efficiency. In addition, the authors adopt the bypassing structure on the CM tree to reduce its switching activity. Experimental results show 19.1% improvement of energy efficiency from prior art.