An Energy Efficient Parallel Architecture Using Near Threshold Operation

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Provided by: University of Miami School of Business Administration
Topic: Hardware
Format: PDF
Sub-threshold circuit design, while energy efficient has the drawback of performance degradation. To retain the excellent energy efficiency while reducing performance loss, the authors propose to investigate near sub-threshold techniques on Chip Multi-Processors (CMP). They show that logic and memory cells have different optimal supply and threshold voltages; therefore they propose to allow the cores and memory to operate in different voltage regions. With the memory operating at a different voltage, they then explore the design space in which several slower cores clustered together share a faster L1 cache. They show that architecture such as this is optimal for energy efficiency. In particular, SPLASH2 benchmarks show a 53% energy reduction over the conventional CMP approach (70% energy reduction over a single core machine).
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