An Error Compensated DCT Architecture with Booth Multiplier

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Provided by: IRD India
Topic: Hardware
Format: PDF
In modern sciences and technologies, images have a broader scope due to growing importance of scientific visualization. Due to this image compression and manipulation is of major interest in research. In this paper, DCT architecture is proposed to deal with the truncation errors and to obtain a high throughput. Compensation architecture is done for the error due to truncation during multiplication to meet the PSNR requirements. An area efficiency and high speed is obtained by the radix 4 Booth multiplier comparing the works on multiplier based DCT.
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