An Error-Correcting Unordered Code and Hardware Support for Robust Asynchronous Global Communication

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Provided by: edaa
Topic: Hardware
Format: PDF
A new delay-insensitive data encoding scheme for global asynchronous communication is introduced. The goal of this paper is to combine the timing-robustness of delay-insensitive (i.e., unordered) codes with the fault tolerance of error-correcting codes. The proposed Error-Correcting Unordered (ECU) code, called zero-sum, can safely accommodate arbitrary skew in arrival times of individual bits in a packet, while simultaneously providing 1-bit correction and 2-bit detection. A systematic code is targeted, where data can be directly extracted from the code words.
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