An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms

Provided by: Virginia Systems
Topic: Hardware
Format: PDF
The authors implement and experimentally evaluate the timeliness and energy consumption behaviors of fourteen state-of-the-art Real-Time Dynamic Voltage and Frequency Scaling (RT-DVFS) schedulers on two hardware platforms. The schedulers include CC-EDF, LAEDF, REUA, DRA, and AGR1, among others, and the hardware platforms include the Intel i5 processor and the AMD Zacate processor. They implemented the schedulers in a real-time Linux kernel and measured their timeliness and energy consumption under a range of workloads including CPU-intensive, memory-intensive, mutual exclusion lock-intensive, and processor-underloaded and overloaded workloads.

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