Science & Engineering Research Support soCiety (SERSC)
Current, floating-point divisor architectures have low frequency, larger area and high latency in nature. With advent of more graphic, scientific and medical applications, floating point dividers have become indispensable and increasingly important. However, most of these modern applications need higher frequency or low latency of operations with minimal area occupancy. In this paper, the authors propose highly optimized pipelined architecture of an IEEE-754 standard double precision floating point divider is designed to achieve high frequency on FPGAs.