An FPGA Based High Speed IEEE - 754 Double Precision Floating Point Adder/Subtractor and Multiplier Using Verilog

Floating Point (FP) addition, subtraction and multiplication are widely used in large set of scientific and signal processing computation. A high speed floating point double precision adder/subtractor and multiplier are implemented on a Virtex-6 FPGA. In addition, the proposed designs are compliant with IEEE-754 format and handles over flow, under flow, rounding and various exception conditions. The adder/subtractor and multiplier designs achieved the operating frequencies of 363.76MHz and 414.714MHz with an area of 660 and 648 slices respectively.

Provided by: Science & Engineering Research Support soCiety (SERSC) Topic: Hardware Date Added: Mar 2013 Format: PDF

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