As chip manufacturing techniques continue to improve, more complex maksystems are being designed. Designing such a large system is not easily done however and much research from both academia and industry is focused on this problem. One of the problems encountered is how to handle the on-chip interconnections between different modules. Network-on-Chip (NoC) has long been seen as a potential solution to the problems encountered when implementing large digital hardware designs. In this paper, the authors describe an open source FPGA based NoC architecture with low area overhead, high throughput and low latency compared to other published works.