An FPGA Logic Cell and Carry Chain Configurable as a 6:2 or 7:2 Compressor

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Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
To improve FPGA performance for arithmetic circuits that are dominated by multi-input addition operations, an FPGA logic block is proposed that can be configured as a 6:2 or 7:2 compressor. Compressors have been used successfully in the past to realize parallel multipliers in VLSI technology; however, the peculiar structure of FPGA logic blocks, coupled with the high cost of the routing network relative to ASIC technology, renders compressors ineffective when mapped onto the general logic of an FPGA.
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